1. Field of the Invention
The present invention relates to the fabrication of semiconductor junction devices, and more particularly, to a method of fabricating a metal-insulator-metal junction having barrier heights adjustable by the composition of the insulator layer.
2. DESCRIPTION OF THE PRIOR ART
The references listed herein are cited because they discuss technical areas such as tunneling, Fermi levels, barriers and techniques for varying their heights and metal-semiconductor-metal junctions.
The references are cited as background art, and do not relate to Fermi level pinning at metal-polycrystalline-metal interfaces and at grain boundaries for controlling the height and shape of barriers.
U.S. Pat. No. 3,056,073 issued Sept. 25, 1986 to Mead entitled SOLID-STATE ELECTRON DEVICES describes a tunnel diode structure wherein two metal plates with an applied electric field are separated by an insulating layer and electrons as one metal plate near the Fermi level tunnel through the conduction band of the insulator into the other metal plate.
U.S. Pat. No. 3,448,350 issued June 3, 1969 to Yamashita et al entitled SEMICONDUCTOR COMPRISING PLURAL DEEP-LEVEL-FORMING IMPURITIES describes a semiconductor device comprising a body of semiconductor material such as a III-V compound, Si or Ge doped with at least two deep-level-forming impurities. At least two electrodes are provided to the semiconductor body. The body may have additional regions of p, n, p+ and n+ conductivity formed therein.
U.S. Pat. No. 3,702,956 issued Nov. 14, 1972 to Renard et al entitled JOSEPHSON JUNCTIONS relates to a Josephson type junction constituted by a layer of semiconductor material inserted between two superconductors. The superconductors are chosen such that the Fermi level of these superconductors falls at the location of the contact with the semiconductor material externally of the forbidden gap of the said semiconductor. Junctions according to the invention may be used in high frequency current applications when a D.C. voltage is applied.
U.S. Pat. No. 4,220,959 issued Sept. 2, 1980 to Kroger, entitled JOSEPHSON TUNNEL JUNCTION WITH POLYCRYSTALLINE SILICON, GERMANIUM OR SILICON-GERMANIUM ALLOY TUNNELING BARRIER, describes a structure wherein a Josephson tunnel junction device having niobium nitride superconductive electrodes includes a polycrystalline semiconductor tunneling barrier therebetween comprised of silicon, germanium or an alloy thereof preferably deposited on the lower superconductive electrodes by chemical vapor deposition. The barrier height of the junction is precisely controlled by precision doping of the semiconductor material.
U.S. Pat. No. 4,371,884 issued Feb. 1, 1983 to Esaki et al, entitled INAS-GASB TUNNEL DIODE, discloses a tunnel diode consisting of an accumulation region of p-type GaSb and an accumulation region of n-type InAs separated by a thin layer of a quaternary compound consisting of InGaSbAs. Such a diode structure converts the interface between the two accumulation regions of p-type and n-type material from what would normally be an ohmic junction into a tunneling junction. Such a tunnel diode requires no heavy doping which is normally required for a tunnel diode.
U.S. Pat. No. 4,449,140, issued May 15, 1984 to Board, entitled SEMICONDUCTOR BARRIER SWITCHING DEVICES, discloses two and three terminal semiconductor barrier switching devices in which a semiconductor junction or a Schottky barrier is used to inject carriers towards a barrier formed by a narrow layer having the same dopant type. In the non-conducting state, the barrier prevents conduction but as an applied bias is increased, the barrier begins to allow carriers of the opposite type to pass releasing the first mentioned carriers and causing the barrier height to be reduced. This action becomes regenerative with increasing bias and after passing through a negative resistance region, the device enters its conducting state. When the third terminal is present, the device is made conducting by biasing its third terminal to cause carriers of the first mentioned type to be injected into the barrier region, for example, from a diffusion adjacent to the third terminal.
U.S. Pat. No. 4,490,733, issued Dec. 25, 1984 to Kroger, entitled JOSEPHSON DEVICE WITH TUNNELING BARRIER HAVING LOW DENSITY OF LOCALIZED STATES AND ENHANCED FIGURES OF MERIT, describes a superconducting tunnel junction device having superconductive electrodes which has a non-homogeneous barrier layer of amorphous semiconducting material with a reduced density of localized states in the central region of the barrier so as to minimize leakage currents, resulting in improved current-voltage characteristics approximating an ideal tunnel junction device. In a preferred embodiment, superconductive electrodes of niobium are conjoined with a tri-layer barrier using pure silicon adjoining the electrodes and a core hydrogenated amorphous silicon.
U.S. Pat. No. 4,763,176, issued Aug. 9, 1988 to Ito entitled METAL-SEMICONDUCTOR-METAL SCHOTTKY PHOTODIODE, describes a metal-semiconductor-metal photodiode comprising a semiconductor layer and a cathode electrode and an anode electrode which are formed on the semiconductor layer and are made of such mutually different electrode materials that the cathode electrode has a Schottky barrier height .PHI..sub.bn from a conduction band satisfying .PHI..sub.bn &gt;Eg/2 and the anode electrode has a Schottky barrier height .PHI..sub.bp from a valence band satisfying .PHI..sub.bp &gt;Eg/2, where Eg denotes the energy band gap.
IBM Technical Disclosure Bulletin, Vol. 16, No. 2, July 1973, page 615, describes a Schottky barrier diode in which the level of the silicon incorporated therein has an effect on the barrier heights.
IBM Technical Disclosure Bulletin, Vol. 18, No. 2, July 1975, page 544, describes a thin film device having increased efficiency which consists of an inexpensive substrate made of aluminum, tungsten, steel, glass and the like. On top of the substrate is a thin film of a semiconductor such as GaP, ZnS, GaN, Al.sub.1-x Ga.sub.x P, and the like. This "intermediate semiconductor layer" should have a relatively good lattice constant match to silicon.
On top of the semiconductor layer is placed a thin layer of polycrystalline silicon. The thickness of the silicon film is of the order of 10 microns. The conductivity type of the silicon and the semiconductor layer on the substrate are of the same type, that is, they are either both N type or they are both P type.
IBM Technical Disclosure Bulletin, Vol 29, No. 5, October 1986, page 2235 discloses a transistor consisting of an InGaAs base sandwiched between two GaAs layers which serve as emitter and collector. A metal on the edge of the structure forms a Schottky barrier and the barrier height to the InGaAs layer decreases with increasing In fraction to the point where the barrier height to the metal goes to zero.
IBM Technical Disclosure Bulletin, Vol. 29, No. 5, October 1986 at page 2244, shows a metal-insulator-metal structure wherein control of the current through the InGaAs insulator is achieved through gate control of the barrier material. The Schottky barrier height of the polycrystalline In.sub.x Ga.sub.1-x As material varies with the composition difference between the Schottky barrier and the metal.
IBM Technical Disclosure Bulletin, Vol 29, No. 5, October 1986 at page 2283 describes a hot electron-type transistor structure constructed with a semiconductor (e.g., nGaAs) for the emitter and collector, and with an epitaxial n++ semiconductor with a smaller band gap (e.g., InGaAs) for the base layer. This will minimize base losses associated with scattering at the metal/semiconductor (base/collector) interface. Further, the emitter/base barrier is made larger than the base/collector barrier to improve the current gain. This is accomplished by grading the In concentration in the ternary semiconductor base layer. The energy bands for the case of a GaAs/InGaAs/GaAs device are shown in which a larger In fraction at the emitter/base interface than at the collector/base interface results in a higher emitter/base barrier. The composition is thus graded so that the In concentration decreases across the base from emitter to collector.
IBM Technical Disclosure Bulletin, Vol. 29, No. 5, October 1986 at page 2299, describes a contact formed using an alloy of a metal with a small percentage of an impurity ingredient. When the alloy is fused with semiconductor material of the heterojunction structure, the metal forms an alloy with one ingredient thereof and the impurity diffuses in snowplow fashion into the heterojunction structure.
When a thin film of Pd-Mg is deposited on GaAs and heated to 500.degree. C., it is converted to PdGa. The Mg diffuses/snowplows into GaAs at the interface, producing a p+ doped layer of GaAs. The use of this material in contacting thin active device layers is illustrated for the three cases: (1) heterojunction hot electron ("metal base") transistor base contact, (2) heterojunction bipolar transistor base contact, and (3) contact to a Modulation Doped Field-Effect Transistor (MODFET) 2D electron gas.
IBM Technical Disclosure Bulletin, Vol. 29, No. 8, January 1987 at page 3662, discloses the use of lattice-matched epitaxial heterostructures in semiconductor devices. Pseudomorphic heterostructures are fabricated with barrier heights which are controlled by composition according to the electron affinity rule.
IBM Technical Disclosure Bulletin, Vol. 29, No. 10, March 1987 at page 4534 describes the use of a ternary alloy of InGaAs (In.sub.1-x Ga.sub.x As) for a collector isolator and the insulation of the surface thereof with a p-n junction to provide the ability to control the barrier height at the base interface while providing general insulation.
IBM Technical Disclosure Bulletin, Vol. 30, No. 6, November 1987 at page 412, discloses a lateral double-heterojunction bipolar junction transistor structure designed for GaAs technology.
The device is fabricated as outlined below:
On a semi-insulating GaAs (Si GaAs) substrate, the following layers are subsequently grown using Molecular Beam Epitaxy (MBE):
p+GaInAs (100 nm thick; doping level: 10.sup.19 cm.sup.-3), PA2 n Al GaAs (50 nm; 10.sup.18 cm.sup.-3), PA2 n+ GaInAs (50 nm; 10.sup.19 cm.sup.-3).
The latter layer serves to provide good ohmic contacts. It is a variable composition layer, starting at the bottom as n GaAs and gradually changing to n+ InAs at the top.
IBM Technical Disclosure Bulletin, Vol. 31, No. 2, July 1988 at page 383 describes a technique whereby ohmic contacts are prepared so as to produce thermally-stable low-resistance contacts. Two preparation methods are described: Indium-Germanium coevaporation and implantation of indium through the contact metals.
Ohmic behavior in the contact material is believed to be due to a reduction of the barrier height, by ternary InGaAs phases, which exist at the metal/GaAs interfaces.
The publication, "Reducing the effective height of a Schottky barrier using low-energy ion implantation" by J. M. Shannon, Applied Physics Letters, Vol. 24, No. 8, Apr. 15, 1974 at page 369 reports that a thin highly doped layer at the surface of a semiconductor has been used to increase the surface field of a Schottky barrier and reduce the barrier height by an amount insensitive to applied bias. The effective barrier height of Ni-Si barriers of this type made using ion-implantation techniques has been reduced by an amount in the range 0-0.2 eV without significant degradation of the reverse characteristic.
The publication "BARRIER HEIGHT CONTROL OF PD.sub.2 Si/Si SCHOTTKY DIODES USING DIFFUSION FROM DOPED Pd" by B. Studer, Solid State Electronics, Vol. 23, pages 1181-1184, discloses that the barrier height of metal-semiconductor contacts can be varied within wide limits by a suitable doping (Sb,A1) of the metal layer itself and application of a temperature treatment to the sandwich structure. As a result, the doping elements are weakly diffused into the semiconductor surface. This leads to a change of the band bending and finally to a change of the barrier height. Pd.sub.2 Si/n-Si diodes with barrier heights q.multidot..PHI..sub..beta. between 0.5 and 0.8 eV were fabricated reproducibly by this method. The barrier height of undoped Pd.sub.2 Si/Si contacts equals 0.72 eV. The doping elements were introduced into the metal layer by partly covering the Pd-cathode of a DC-sputtering apparatus with A1 or Sb, and subsequent sputtering of the composite cathode onto the silicon slices.
The concentration of doping elements in the sputtered metal layer is given by the relation of the part of the cathode surface covered with the doping element to the whole cathode surface.
The publication "Absence of Fermi Level pinning at metal-In.sub.x Ga.sub.1-x As (100) interfaces" by L. J. Brillson et al, Applied Physics Letters, V. 148, No. 21, May 26, 1986 at page 1458 discloses that soft x-ray photoemission spectroscopy measurements of clean, ordered In.sub.x Ga.sub.1-x As (100) surfaces with Au,In,Ge or A1 overlayers reveal an unpinned Fermi level across the entire In alloy series. The Fermi level stabilization energies depend strongly on the particular metal and differ dramatically from those of air-exposed interfaces. This wide range of Schottky barrier height for III-V compounds is best accounted for by a chemically induced modification in metal-alloy composition.